The present invention relates to a manufacturing technology of a semiconductor device, in particular, to a technique effective when applied to the manufacture of a semiconductor element having a nickel silicide layer.
With increasing integration density of semiconductor devices, field effect transistors (Metal Insulator Semiconductor Field Effect Transistors) are miniaturized according to the scaling rule. The miniaturization of field effect transistors however does not lead to a high-speed operation because of an increase in the resistance of a gate or source and drain. For example, in field effect transistors having a gate length of 0.2 μm or less, a salicide technology of forming a low-resistance silicide layer, for example, a nickel silicide layer or cobalt silicide layer in self alignment over the surface of a conductive film constituting a gate or over the surface of semiconductor regions constituting the source and drain, thereby reducing the resistance of the gate or source and drain is under investigation.
When a natural oxide film is present on the surface of a film or the like over which a silicide layer is formed (for example, a conductive film constituting a gate and semiconductor regions constituting source and drain), however, the resistance of the silicide layer becomes uneven. Prior to the formation of the silicide layer, therefore, the surface of the film or the like over which the silicide layer is formed is washed to remove therefrom the natural oxide film or impurities.
In Japanese Patent Laid-Open No. 2002-93739 (Paragraph [0008], Paragraph [0009], FIG. 1), described is a technology including, prior to the salicide step, a step of carrying out reactive plasma treatment with reactive plasma for causing a reduction reaction over the substrate in the cleaning step performed over the substrate.